First, the outline of data transmission system will be given. FIG. 2 is a diagram showing a typical configuration of a data transmission system comprising echo cancellers. In FIG. 2, a structural example of a transmission system (full duplex transmission system) using a twisted pair cable is shown as a data transmission system to which a canceller circuit relating to the present invention may also be applied.
Referring to FIG. 2, in a transmission device of this data transmission system, each transmission symbol (digital signal) is converted into an analog signal by digital-to-analog converters 10 and 20, driven out by driver circuits 11 and 21, and transmitted to a transmission line 30 via hybrid circuits 16 and 26, and transformers 17 and 27. A transmission signal sent from the opposite device to the transmission line 30 is received by a receiver device via the transformers 17 and 27, and the hybrid circuits 16 and 26. In the receiver device, after the received analog signal is converted into a digital signal by analog-to-digital converters 12 and 22, the waveform is equalized by waveform equalizers 13 and 23, and then a received symbol is output from identifiers not shown in the drawing. In the transmission line 30, a transmission signal and a received signal are simultaneously and bi-directionally transmitted. An echo occurs when a transmission signal sneaks into a received signal, and it is caused by mismatches among the transformers 17 and 27, and the hybrid circuits 16 and 17, and mismatches between the connectors of the transmission line 30.
The echo cancellers 14 and 24 receive the transmission symbols and error signals obtained by subtractors 15 and 25 which subtract the output of echo cancellers 14 and 24 (echo hereplica) from the output of the analog-to-digital converters 12 and 22 respectively, so that the echo and noise such as near-end cross-talk (NEXT) are cancelled.
As a concrete example of the data transmission system, for instance, “IEEE Standard 802.ab 10000BASE-T” specifies the physical layer (PHY) for Gigabit Ethernet (Registered Trademark) over CAT-5 cabling systems where, for every incoming data byte, a trellis encoder outputs four PAM-5 symbols to four pairs of wires at 125 MBaud/s. Signals are transmitted bi-directionally on each of the four wires (four pairs of the transmission line in FIG. 2), therefore echo must be removed on each wire. In addition, near-end cross-talk (NEXT) from the other wires can also be removed in a way similar to removal of echo cancellation (refer to Non-Patent Document 1: Runsheng, et al., “A DSP Based Receiver for 1000BASE-T PHY,” IEEE International Solid State Circuits Conference 19-6, 2001). In Non-Patent Document 1, the configuration of a DSP based receiver for 1000BASE-T physical layer (PHY) shown in FIG. 12 is disclosed. Although a data path shown in FIG. 12 is only for one channel, all four channels have similar structure.
Referring to FIG. 12, a block before a 9-bit pipeline analog-to-digital (A/D) converter 607 includes a hybrid 603, a baseline wander correction circuit 604, a programmable gain stage 605, and an anti-aliasing analog low-pass filter (LPF) 606. The hybrid 603 performs coarse echo cancellation by subtracting a replica of a band-limited waveform from a received waveform. Residual echo is removed by a digital echo canceller (ECHO & NEXT) 610. Since the discrete-time response of echo is sensitive to timing phase of the A/D converter 607, the ECHO & NEXT canceller 610 has jitter noise caused by timing jitter. The LPF 606 reduces the jitter noise by removing the high-frequency component of echo and near-end cross-talk responses. The baseline wander correction circuit 604 removes baseline distortion caused by the low-cut nature (the high-pass nature) of the transformer, and is controlled by a decision directed adaptive loop. A FIFO (First-In First-Out circuit) 608 provides compensation for delay skew on four different wires. The output signals of the A/D converter 607 are written into the FIFO 608 on A/D sampling clocks with different phases for four different channels, and are read on a single clock (that clocks all DSP blocks). Putting the FIFO 608 before the DSP block, resolves the latency skew at the earliest stage, and all DSP blocks operate on the same clock domain. The delay of the FIFO 608 on each channel is found by matching the idle symbol on all four channels during start up. The delay of the FIFO 608 is determined by the maximum delay skew. The digital ECHO & NEXT canceller 610 removes NEXT (near-end cross-talk) as well as the residual echo of the hybrid. The ECHO & NEXT canceller 610 for each channel is implemented by four FIR (Finite Impulse Response) filters (three for NEXT (20×3 taps), one for echo (160 taps)), and local transmitted data (TX data) from an encoder 602 is supplied to the FIR filters. A delay circuit (Delay Adjust) 611 at the input of the ECHO & NEXT canceller 610 matches the path delay from the input of the A/D converter 607 to the output of the FIFO 608. Each tap of the FIR filter in the ECHO & NEXT canceller 610 is adaptive. Since changes of responses are slow compared to the 125 M/s symbol rate, the loop gain of the ECHO & NEXT canceller is set to a small value to reduce gradient noise. A least mean-square (LMS) algorithm is used for adapting taps of the ECHO & NEXT canceller 610. The output (echo and cross-talk replica) of the ECHO & NEXT canceller 610 is subtracted from the output of the FIFO 608, and the result is supplied to a feed-forward equalizer (FFE) 612. The FFE 612 is a filter for canceling the pre-cursor ISI (InterSymbol Interference). The output of the gain stage is fed to a DFSE (Decision Feedback Sequence Estimation) 614. The DFSE 614 implements a trellis code decoder and a DFE (Decision Feedback Estimator). To generate branch metrics of the trellis code decoder, the absolute value of error is used. To compare the gain of the DFSE 614, a 5-level threshold detector is implemented. Digital timing recovery (not shown in the drawing) controls the sampling phases of the A/D converter 607. The digital timing recovery includes a phase loop for each channel and a frequency loop shared by all four channels. Note that reference symbols 615, 616, 617, and 618 indicate error generator, error monitor, adaptation algorithm, and control circuit respectively, however, since they are not directly relevant to the subject of the present invention, explanations of them will be omitted.
FIG. 13 is a diagram illustrating the configuration of the ECHO & NEXT canceller 610 shown in FIG. 12. FIG. 13 is newly created by the present inventor in order to describe the prior art in more detail. As shown in FIG. 13, it comprises an echo canceller 702 (for instance a 160 tap FIR filter) which receives a transmission symbol pair 1 and a residual echo and outputs an echo replica, and three NEXT canceller circuits 703, 704, and 705 (20 tap FIR filters). Out of four pairs of twisted pair cables, an echo error signal from a twisted pair 1, near-end cross-talk from a twisted pair 2, near-end cross-talk from a twisted pair 3, and near-end cross-talk from a twisted pair 4 are sneaked into an input signal pair 1 from the twisted pair 1. The transmission symbol and the error signal (residual echo) are supplied to the echo canceller 702, its output is supplied to a subtractor 706 and subtracted from an output waveform of an A/D converter 701. The output of the subtractor 706 (the waveform obtained by subtracting the echo replica from the received waveform) is supplied to a subtractor 707, and the subtractor 707 subtracts the outputs of the NEXT canceller circuits 703, 704, and 705 from it, outputting the result as an error signal. The NEXT canceller circuits 703, 704, and 705 receive transmission symbol pairs 2, 3, and 4, respectively, and the error signal in common. The NEXT canceller circuits 703, 704, and 705 adaptively control respective tap coefficients according to the LMS algorithm and respectively generate the cross-talk replicas. Note that near-end cross-talk (NEXT) means cross-talk between a signal pair (twisted pair) within the same cable. Echo can be considered to be cross-talk between the same pair (twisted pair).
In recent years, as the transmission speed of transmission system increases, high speed and high accuracy A/D converter is demanded for the receiver device shown in FIG. 2. Increasing the speed of A/D converter means increasing conversion rate (sampling frequency), and in order to realize high accuracy in A/D converter, not only DC characteristics such as resolution, offset, and linearity need to be improved, but also the improvement of dynamic characteristics (A/D converter characteristics) such as reducing sampling clock skew is necessary. The resolution of high-speed A/D converter is relatively coarse, and- it is difficult and expensive for an A/D converter to be high speed and high accuracy. Therefore, in order to realize a high-speed and high-accuracy A/D converter, an architecture in which a plurality of A/D converters are arrayed and each A/D converter operates in a time-interleaved system (called “interleaved A/D converter system” or “time-interleaved A/D converter system”) has been conventionally employed (refer to Non-Patent Document 2 for instance). In an interleaved A/D converter system, high-speed operation is achieved while suppressing the increase in the conversion rate of each A/D converter by driving a plurality of A/D converters connected in common to an analog input terminal with multi-phase frequency-divided clock signals having respective phases spaced apart.
FIG. 11 illustrate a model of a noise occurrence caused by phase shift, and is a diagram for schematically explaining how noise caused by the phase sift of sampling clocks between two A/D converters occurs in an interleaved A/D converter system of two A/D converters. In FIG. 11, the abscissa indicates time and the ordinate signal amplitude. Further, in FIG. 11, timings indicated by phase 1 show the sampling phases of the first A/D converter, and phase 2 shows the ideal sampling phases of the second A/D converter when phase 2 is a reference phase. An analog signal in FIG. 11 shows the waveform of a time-continuous analog signal fed to the two A/D converters as an input signal, and intersections of the analog signal waveform and the timings indicated by the phases 1 and 2 show time-discrete sample values (the ideal sample values) of the first and second A/D converters. Further, in FIG. 11, timings indicated by respective arrows (designated by ‘phase shift’) are the timings at which the sampling phase of the second A/D converter is shifted by the phase shift of the sampling clock. The phase shift of the sampling clock is termed a sampling phase shift.
As shown in FIG. 11, the sampling phase of the second A/D converter is shifted by a sampling phase shift, and as a result, a difference between the sampled value under the condition when a sampling phase shift exists and the ideal sample value (the intersection of the A/D converter 2 and the analog signal) occurs (refer to noise indicated by arrows). Here, when the sampling phase shift is Δt, the amplitude of the noise ΔV is given by ΔV=[df (t)/dt] Δt (where f(t) is the time-continuous analog signal waveform), the amplitude depends on the value of the sampling phase shift Δt, and it increases in the area where the differential coefficient df(t) of the signal waveform variation rate f(t) increases (where the slew rate increases).
In order to cope with such a phase shift, a correction circuit correcting the phase shift is provided in a conventional interleaved A/D converter system (refer to Patent Document 1 for instance).
[Non-Patent Document 1]
Runsheng, et al., “A DSP Based Receiver for 1000BASE-T PHY,” IEEE International Solid State Circuits Conference 19-6, 2001.
[Non-Patent Document 2]
Robert Talt, et al., “A 1.8V 1.6 G Sample/s 8-b Self-Calibrating Folding ADC with 7.26 ENOB at Nyquist Frequency,” IEEE International Solid State Circuits Conference 14.1, 2004.
[Non-Patent Document 3]
Simon Haykin, trans. Hiroshi Suzuki, et al., “Adaptive Filter Theory,” Kagaku Gijutsu Shuppan, 508 p.
[Patent Document 1]
U.S. Pat. No. 6,522,282 B1 FIG. 3